The present invention relates to an analysis method and an analysis apparatus for arranging test points in an optimum manner in order to make it easy to test a logic circuit composed of a plurality of elements, and also relates to a semiconductor integrated circuit having an improved arrangement of test points.
One of technologies for easily testing a semiconductor integrated circuit involves a method where test points are inserted in the circuit. The test points are classified into a "1 control point" for improving the ease in controlling a signal line to 1 (hereinafter referred to as "1 controllability"), a "0control point" for improving the ease in controlling a signal line to 0 (hereinafter referred to as "0 controllability ") and an "observation point" for improving the ease in observing a signal value of a signal line (hereinafter referred to as "observability").
A circuit having test points and a method of analyzing positions for inserting the test points are described in detail in an article entitled "Test Points Insertion for Scan-Based BIST" by B. Seiss et al. in Proceeding of 2nd European Test Conference , pages 253 to 262 (1990), or in Japanese Patent Application Laid-Open No. 6-331709 entitled "Circuit improved in testability and method of improving testability of circuit".
Particularly, the method of analyzing test points as described in the former B. Seiss et al reference defines an objective function (hereinafter, referred to as "test cost") using a probabilistic testability scale, referred to as a so-called COP controllability observability procedure), and determines test points one by one so as to minimize the objective function. That is, the procedure to determine one test point comprises the steps of selecting candidates for a test point (hereinafter, referred to as "test point candidates") based on an approximation value of the test cost when the test point candidate is inserted, calculating an actual test cost when each of the test point candidates is inserted, and then determining a test point candidate which minimizes the test cost as a test point. This process is repeated for the number of a test points. It has been confirmed that this analysis method is effective for simplifying a random number pattern test.
Further, a method of analyzing test points which improves the above method by B. Seiss et al. so as to suppress degradation in a signal delay due to test point insertion is described in an article entitled "Timing-Driven Test Point Insertion for Full-Scan Partial-Scan BIST" by K. -T. Cheng et al. in Proceeding of International Test Conference, pages 506 to 514 (1995). In the procedure for obtaining one test point in the above method by B. Seiss et al., the Cheng et al method calculates a margin of signal delay in each signal line of a circuit, and requires a condition of the test point candidate that the margin of signal delay be larger than a predetermined value. The other processes are the same as those in the method of B. Seiss et al. Therein, the margin of signal delay in a path between terminals or elements refers to a value obtained by subtracting an actual signal delay from an allowable design signal delay. The margin of signal delay in each signal line is a minimum margin of signal delay in a path containing it.
Among the above-mentioned conventional methods of analyzing test points, the method of B. Seiss et al. has a problem in that the performance of a semiconductor integrated circuit is degraded by degradation of a signal delay due to test point insertion. On the other hand, in the method of Cheng et al, since it is required to calculate margins of signal delay for individual signal lines every time one test point is selected, due to a bottleneck in this process there is a problem in that the processing cannot be completed within a practical time for a large scale logic circuit.
Further, as a method of actually forming a test point in a semiconductor integrated circuit, it is common to insert a 2-input OR gate when a 1-control point is formed, and to insert a 2-input AND gate when a 0-control point is inserted. However, in this case, most of the semiconductor integrated circuits after, inserting a test point, are circuits having problems which should be optimized from the viewpoint of the overhead of the signal delay and the circuit area.
The methods of analyzing test points as described above have a problem in their practical use since the processing time is very long when a large scale logic circuit is analyzed. Most of the processing time is spent in test cost calculation of test point candidates in which the loop-nest becomes deepest. Assuming that the number of test point candidates and the number of test points are proportional to the number of gates, the test cost calculation time is proportional to the number of gates in a worst case, and the processing time for the total test point analysis is proportional to the third power of the gate number. On the other hand, from the viewpoint of the trend toward producing semiconductor integrated circuits of larger scale and the trend toward improving the processing speed of computers, it is preferable that the practical processing time is proportional to the second or less power of the gate number.
Further, a problem of inserting the test point in a semiconductor integrated circuit concerns occurrence of overhead in a circuit area, the main cause of which is in input elements solely used for a test point and flip-flops with a scan function used as output element.